Recent demands for low power consumption, large integration density and high speed in semiconductor integrated circuit devices (chips) have required remarkable reduction in power supply resistance or significantly lowering resistance of power supply lines.
Moreover, standard cell methodology is widely employed in chip designing. Japanese Patent Kokai Publication No. JP-H10-041393A, which is incorporated herein by reference thereto, describes, as a power supply system for a standard cell, a power supply line formed along the cell rack (cell array) and a power supply bridge line arranged perpendicular to the power supply line.
The inventors of the present disclosure have carefully analyzed the power supply line system to further reduce the resistance thereof and have thus discovered the following problems, which will be described with reference to FIGS. 1 to 5 indicative of a prototype power supply line system conceived by the inventors.
FIG. 1 is a diagram illustrating a definition of regions A0 to A3 that appear in the following description. The regions A0 to A3 are defined as shown in FIG. 1, in a layout diagram of a semiconductor integrated circuit device. Here, the region A0 is a region in which input/output PADs are disposed, and this region is a power supply source. The region A1 is a region in which a power supply protection device, an input/output protection device, or an output transistor is disposed, as a measure against ESD (Electrostatic Discharge) or latch-up. An output transistor or a circuit device controlling the transistor is disposed in the region A2. The region A3 is a region in which a logic circuit, which operates by a power supply different from the region A1 and the region A2, is disposed. FIG. 2A to FIG. 11 below respectively illustrate regions enclosed by solid lines in FIG. 1.
FIGS. 2A to 2C are diagrams showing a layout of prototype power supply lines, which employs a multi-level wiring structure including a first-level wiring (metal) layer, a second-level wiring (metal) layer formed over the first-level metal layer with an intervention of a first interlayer insulating film therebetween, and a third-level wiring (metal) layer formed over the second-level metal layer with an intervention of a second interlayer insulating film therebetween. Referring to FIG. 2A, as a second-level metal layer above a cell rack (cell array) (not shown in the diagram), a pair of power supply lines formed of a GND power supply line W111 and a VDD power supply line W112 are arranged along the cell rack. Furthermore, as a third-level metal layer, a pair of power supply lines formed of a GND power supply line W113 and a VDD power supply line W114 are arranged. Here, the GND power supply line W113 is arranged above the GND power supply line W111. Meanwhile, the VDD power supply line W114 is arranged above the VDD power supply line W112.
FIG. 2B is an enlarged layout diagram of a region enclosed by a solid line in FIG. 2A. FIG. 2C is a cross-sectional diagram along a path A-A′ of FIG. 2B. In FIG. 2A and FIG. 2B, “X” indicates contacts between the first-level metal layer and the second-level metal layer, and filled circles indicate contacts between the second-level metal layer and the third-level metal layer. By having regular contacts between the second-level metal layer and the third-level metal layer, the GND power supply line W111 and the GND power supply line W113 are connected, and also the VDD power supply line W112 and the VDD power supply line W114 are connected, and wiring resistance of these power supply lines is reduced.
In a configuration shown in FIGS. 2A to 2C, a GND power supply line W111 provided as a second-level metal layer and a GND power supply line W113 provided as a third-level metal layer convey the same ground voltage. Furthermore, a VDD power supply line W112 provided as the second-level metal layer and a VDD power supply line W114 provided as the third-level metal layer convey the same power source voltage. In this case, a problem occurs when power supply main lines are interconnected. A description is given below concerning this problem, making reference to FIG. 3 to FIG. 5.
FIG. 3 illustrates a layout in a case where a power supply main line M101 and a power supply main line M102 are connected by a first-level metal layer. Referring to FIG. 3, the power supply main line M101 has the GND power supply lines W111 and W113, and the VDD power supply lines W112 and W114, and has a configuration similar to FIGS. 2A to 2C. Similarly, the power supply main line M102 has VDD power supply lines W121 and W123, and GND power supply lines W122 and W124, and has a configuration similar to FIGS. 2A to 2C.
In the configuration of FIG. 3, in a case where a VDD power supply line included in the power supply main line M101 and a VDD power supply line included in the power supply main line M102 are connected via the first-level metal layer, as shown in FIG. 3, the VDD power supply line W123 and the VDD power supply line W114 are connected via wiring W131 provided as the first-level metal layer. “X” in FIG. 3 illustrates contacts connecting the VDD power supply line W123 and the wiring W131, and contacts connecting the VDD power supply line W114 and the wiring W131. In this case, a circuit (cell) cannot be disposed in two regions B1 and B2 that are enclosed by sold lines in FIG. 3.
Meanwhile, FIG. 4 illustrates another layout in a case where the power supply main line M101 and the power supply main line M102 are connected by the first-level metal layer. Referring to FIG. 4, the power supply main line M101 includes the GND power supply lines W111 and W113, and the VDD power supply lines W112 and W114, and has a configuration similar to FIGS. 2A to 2C. Similarly, the power supply main line M102 includes the VDD power supply lines W121 and W123, and the GND power supply lines W122 and W124, and has a configuration similar to FIGS. 2A to 2C.
In the configuration of FIG. 4, in a case where a VDD power supply line included in the power supply main line M101 and a VDD power supply line included in the power supply main line M102 are connected via the first-level metal layer, as shown in FIG. 4, the VDD power supply line W123 and the VDD power supply line W114 are connected via wiring W132 provided as the first-level metal layer. “X” in FIG. 4 illustrates contacts connecting the VDD power supply line W123 and the wiring W132, and contacts connecting the VDD power supply line W114 and the wiring W132. In this case also, similar to the case shown in FIG. 3, a circuit (cell) cannot be disposed in two regions C1 and C2 that are enclosed by sold lines in FIG. 4. In addition, a problem occurs in that wiring resistance increases with the distance the wiring W132 extends as shown in FIG. 4.
FIG. 5 illustrates a layout in a case where the power supply main line M101 and the power supply main line M102 are connected by a second-level metal layer. Referring to FIG. 5, the power supply main line M101 includes the GND power supply lines W111 and W113, and the VDD power supply lines W112 and W114, and has a configuration similar to FIGS. 2A to 2C. Similarly, the power supply main line M102 includes the VDD power supply lines W121 and W123, and the GND power supply lines W122 and W124, and has a configuration similar to FIGS. 2A to 2C.
In the configuration of FIG. 5, in a case where a VDD power supply line included in the power supply main line M101 and a VDD power supply line included in the power supply main line M102 are connected via the second-level metal layer, as shown in FIG. 5, the VDD power supply line W123 and the VDD power supply line W114 are connected via wiring W133 provided as the second-level metal layer. In this ease, there is a problem in that, in four regions D1 to D4 enclosed by solid lines, the GND power supply line W111 and the GND power supply line W122 provided as the second-level metal layer are not connected, and resistance increases.